by Afifi, SM, Wahba, AM and Wahdan, A-E
Abstract:
To meet the MPEG requirements for high data throughput essential for the recent multimedia applications, new data memory organizations are required. In this paper, a scalable memory organization is proposed to accelerate access to randomly rectangular blocks of visual data to be processed as fast as possible. In the proposed design, we load the video frame pixels stored in traditionally linearly addressable memory as a scan-line manner into a two-dimensional accessible memory, which is organized from a x b memory modules in order to access the entire pixels of the block simultaneously, in parallel. So it is more efficient for multiple blocks access to use the 2D data storage than using the traditionally linearly addressable memory. A module assignment function and an address assignment function are proposed to access any aligned or non-aligned block from the memory modules. The proposed design is implemented and mapped onto an FPGA as a case study. Synthesis results indicate that a scalable, cost-effective design is implemented. High performance is achieved, as at reasonably small hardware costs, considerable speedups of up to 20 thousand times can be expected for the hardware implementation versus the software implementation of the proposed memory organization. ©2010 IEEE.
Reference:
Accelerated access to visual data in multimedia applications (Afifi, SM, Wahba, AM and Wahdan, A-E), In Proceedings, ICCES’2010 – 2010 International Conference on Computer Engineering and Systems, 2010.
Bibtex Entry:
@inproceedings{afifi2010acceleratedapplications,
author = "Afifi, SM and Wahba, AM and Wahdan, A-E",
booktitle = "Proceedings, ICCES'2010 - 2010 International Conference on Computer Engineering and Systems",
pages = "172--177",
title = "Accelerated access to visual data in multimedia applications",
year = "2010",
abstract = "To meet the MPEG requirements for high data throughput essential for the recent multimedia applications, new data memory organizations are required. In this paper, a scalable memory organization is proposed to accelerate access to randomly rectangular blocks of visual data to be processed as fast as possible. In the proposed design, we load the video frame pixels stored in traditionally linearly addressable memory as a scan-line manner into a two-dimensional accessible memory, which is organized from a x b memory modules in order to access the entire pixels of the block simultaneously, in parallel. So it is more efficient for multiple blocks access to use the 2D data storage than using the traditionally linearly addressable memory. A module assignment function and an address assignment function are proposed to access any aligned or non-aligned block from the memory modules. The proposed design is implemented and mapped onto an FPGA as a case study. Synthesis results indicate that a scalable, cost-effective design is implemented. High performance is achieved, as at reasonably small hardware costs, considerable speedups of up to 20 thousand times can be expected for the hardware implementation versus the software implementation of the proposed memory organization. ©2010 IEEE.",
doi = "10.1109/ICCES.2010.5674848",
isbn = "9781424470426",
keyword = "Linear addressing",
keyword = "Memory modules",
keyword = "Module assignment function",
keyword = "MPEG",
keyword = "Rectangular block addressing",
keyword = "Scan-line alignment",
language = "eng",
}